1. Field of the Invention
The present invention relates to a technique of removing a DC offset superimposed on a demodulation signal in connection with a deviation between transmitted and received frequencies.
2. Description of the Related Art
In the receiver using an FSK (Frequency Shift Keying) modulation scheme, such as a digital wireless receiver for a 400 MHz band, demodulation is performed by means of a frequency-voltage conversion, and voltages having respective levels corresponding to a plurality of frequencies, such as binary or quaternary-coded frequencies, are output as a demodulation signal, wherein a DC offset is superimposed on the demodulation signal in connection with a deviation between transmitted and received frequencies. Therefore, a method designed to remove the DC offset using a high-pass filter, and a method designed to extract the DC offset using a low-pass filter and subtract the DC offset from a demodulation waveform, have heretofore been employed.
In the method using a high-pass filter, while a demodulation signal having a certain constant DC component is obtained when the same symbols continue, the DC component will be lost through the high-pass filter to cause deterioration in sensitivity. In the method using a low-pass filter, it is necessary to set a passband of the low-pass filter to a value far less than a symbol rate, so that a sample amount (calculation amount) in a signal processing will be increased.
Therefore, in order to cope with the above problems, there have been proposed techniques disclosed, for example, in JP 11-298542A, JP 3674745B and JP 2006-94245A. These conventional techniques are generally designed to determine a correction amount from an average value of maximum and minimum values in received symbol values to perform a correction for a center frequency.
In a center-error detection/correction circuit disclosed in JP 11-298542A, by utilizing a fact that a binary (2-level) bit synchronization signal has a cycle period of 2/(baud rate)·sec, a received synchronization signal is sampled at intervals of 1/(baud rate)·sec, i.e., two times at an interval of 180 degrees. The obtained two sample values are averaged by a hold capacitor, and an offset value is calculated from the average value. Then, the offset value is subtracted from a baseband signal. In this way, an error in a center level is detected to perform a correction for a center frequency.
In an offset voltage correction circuit disclosed in JP 3674745B, a received baseband signal is sampled (A/D converted), and maximum and minimum values in the sample values for each given time period are detected to derive a median value thereof. Then, the median value is subtracted from the received baseband signal after the A/D-conversion. Further, a variation in the median value per the given time period is derived, and the given time period is set to become shorter as an amount of the variation becomes larger. In this way, a DC component (DC offset) of the baseband signal having large electric power even in a low-frequency range is removed without damaging a waveform. In addition, the offset removal is performed at a high speed, so that a time to data reading is reduced.
In a semiconductor circuit device disclosed in JP 2006-94245A, discrimination regarding an offset is performed by amplifying and converting a received signal into an intermediate frequency signal, subjecting the intermediate frequency signal to analog/digital conversion, subjecting the analog/digital converted signal to quadrature demodulation, extracting respective bands of I and Q components by a filter, subjecting the extracted bands to frequency-voltage conversion, deriving maximum and minimum values of the frequency-voltage converted signal, and discriminating the frequency-voltage converted signal using an intermediate or median value of the maximum and minimum values as a discrimination threshold. In the Patent Document 3, it is also disclosed that a given gain is multiplied to an offset value in order to prevent the circuit from entering an oscillation state even if a large offset value is erroneously calculated due to noise.
The above conventional techniques can reduce a calculation amount to about 1/20 to ⅛ as compared with the method using a filter to extract a DC offset. However, each of the conventional techniques is premised on binary (2-level) codes. Thus, each of the codes corresponds to a respective one of the maximum and minimum values, so that, if a change in signal level occurs, it is possible to take measures by the aforementioned corrections. However, considering the use in ternary or higher multi-ary codes to effectively utilize a limited radio wave resource, even if a change in signal level occurs, it is difficult to recognize which of the codes corresponds to each of the maximum and minimum values as reference values for the correction. For example, in quaternary codes “00”, “01”, “10”, “11”, when an offset correction is performed based on two codes which are not across a median value, such as “00” and “01”, or “10” and “11”, or two codes which are across a median value but not equal in terms of a deviation from the median value, such as “00” and “10” or “01” and “11”, a frequency deviation is not accurately detected so that it becomes impossible to synchronize a received frequency with a transmitted frequency or to demodulate a symbol. Although a possibility to accurately detect the maximum and minimum values becomes higher if a signal level is monitored for a long period of time, it will take time for demodulation of a symbol, e.g., before starting an audio output.